This invention relates to logic circuits configured with field effect transistors, more particularly to logic circuits configured with field effect transistors to form a latch and in particular, a shift register latch.
An example of the prior art shift register latch 100 is provided in FIG. 241, in which there is a first latch stage 1 and a second latch stage 11. The first latch stage receives inputs in the form of data to a combination logic circuit, which in the case of FIG. 1, is an AND-OR combination 3 and at the occurrence of clock 2, the data on terminal 2 is loaded into a master latch 5 or at the occurrence of clock 1 the data on terminal 4 is loaded into the master latch 5. The master latch 5 stores the data and provides a representative sample of the data that's stored therein on its output terminal 6, which at the occurrence of clock 3 is loaded into a slave latch 7. The master latch 5 stores the data internally until the occurrence of a clock 3, when it is stored in the slave latch 7. The slave latch 7 stores the data, as well as provides a representative sample of the stored data on output terminal 9 and shift terminal 8 for application to the second stage shift register latch 11. The second stage shift register latch 11 includes an input combination circuit 13, which in the embodiment of FIG. 1, is an AND-OR combination, a master latch 15 and a slave latch 17. The master latch 15, at the occurrence of either clock 1 or 2 will store either the data that is on terminal 10 or 8, respectively, and present a representation thereof on terminal 12 for application to the slave latch 17, which will store the logic level that is present on terminal 12 at the occurrence of clock 3, and present a representation thereof on its output terminal 14.
In FIG. 2, to which reference should now be made, there is illustrated a waveform diagram of the shift register latch of FIG. 1, which is, in the embodiment shown in FIG. 1, a prior art representation of a level sensitive, shift register latch. There are 3 clocks provided to the shift register latch necessary for the shift register latch 100 of FIG. 1 to operate. They are clocks 1 and 2, which store the data into the master latches 5 and 15, and clock 3, which loads data into the slave latches 7 and 17. Clocks 1 and 2 are represented by waveform 20, and clock 3 is represented by waveform 22.
The shift register latch disclosed in FIG. 1 requires the multiple clocking arrangements that are indicated in FIG. 2, and requires that in the combination logics 3 and 13 decisions must be completed by the trailing edge of clock 1 that is represented by waveform 20. This creates a problem in dynamic field effect transistor logic when clock 3 is to be used to discharge the last stage of the combination logic, which is a necessary requirement for speed enhancement of the device. Therefore, the prior art shift register latch is limited and unsuitable for high-speed applications.